The present invention relates to a lock control apparatus and method, and more particularly to a lock control apparatus and method for a computer system, which includes a plurality of banks, each paired system of which has a plurality of store-in cache memories (SICs) which share a main memory. Each of the caches of the paired system is used by at least one central processing unit, respectively, and is connected to another cache of the paired system through a bus.
In a shared-memory multi-processor system, a plurality of processors share a main memory. In such a system, a certain processor must exclusively use data in a certain shared area of the main memory for a certain time period. For example, when the processor executes an operation of adding "1" to data in the certain shared area, during a sequence of processing conducted since data in the shared area is read out to add "1" until the data is again written in the shared area, other processors must be prohibited from accessing to that data. Without such prohibition, updating data and thus accessing updated data are not ensured.
In order to ensure exclusive access and thus to prohibit the other processors from accessing the data, a lock variable is typically used. In gaining access to the shared area of the main memory, the lock variable must be checked to confirm that the lock variable is not in a "lock" status. The lock variable check is conducted in accordance with a lock request, and when the lock variable is in an "unlock" status, then the lock variable is updated to the "lock" status. Then, access is permitted to a corresponding shared area. After the exclusive processing is finished, the lock variable is returned to the "unlock" status in accordance with an unlock request. Such control is called a "lock control".
When a cache memory (e.g., a first cache memory) is provided in each processor, if an inconsistency occurs between the contents of the main memory and the contents of the cache memory, corresponding data in the cache memory must be invalidated. Such a processing is called "cache consistency processing".
For example, when a certain processor rewrites the contents in the shared area from "0" to "1", unless corresponding data in the cache memories of other processors is invalidated (e.g., nullified), the other processors unintentionally and erroneously read out old data, that is, "0". Hence, that data is invalidated through the cache consistency processing so as to be "flushed" (e.g., removed) from the cache memory. Then, other processors read data in the main memory because of a cache "miss", since the processors are capable of reading data after updating, that is, a "1".
In this example, when a certain processor A acquires a "lock" in accordance with the lock request, all the cache consistency processing with respect to corresponding shared areas must be completed. Without the processing, a data updating operation which has been conducted with respect to the shared areas by other processors B is not ensured.
Hence, a conventional lock control apparatus has a request buffer which ensures an order of requests. A "reply for lock" (e.g., a lock reply) is stored in a last entry of the request buffer.
In the conventional lock control apparatus, when a lock is to be acquired in the secondary cache which has been divided into a plurality of banks, two conventional methods are used as described below.
In a first method, a processor issues lock requests to all banks concurrently until the processor acquires locks from all the banks. However, in this first method, when a plurality of processors issue a lock request to the same lock address, respectively, and when a different processor obtains a lock in each bank, an unlock request and a lock request must be repeated since each central processing unit releases the lock thus acquired once until it issues a lock request again and the lock succeeds in all the banks. This is cumbersome and problematic in that the time required for acquiring a lock at the time of lock conflict at the same address is increased.
In a second method, a processor issues a lock request to a certain bank. After acquisition of the lock, the processor issues cache consistency requests to all the banks. However, in this second method, a cache memory in the processor cannot be accessed until a reply to the cache consistency request is returned from all the banks.
That is, even though a result of a lock request is found in accordance with a lock reply from a certain secondary cache, because it cannot be ensured that the cache consistency processing for the shared area has been completed, a first cache cannot be accessed until a reply to a request for a cache consistency guarantee is returned from all the secondary caches. Hence, access to the shared area is delayed until replies to the request for the cache consistency guarantee are returned from all the banks of the secondary cache although the lock acquisition has been completed.